The present invention relates to a wiring substrate having a plurality of integrated circuit chips mounted thereon and interconnecting input and output signals of the integrated circuit chips and an electronic circuit apparatus using the wiring substrate, and in particular to a wiring substrate suitable for a large-sized logical unit such as a computer requested to have a higher signal propagation speed and an electronic circuit apparatus using such a wiring substrate.
For raising the operation speed in computers or the like, it is necessary to not only raise the operation speed of integrated circuits but also shorten signal propagation delay time within a wiring substrate having a plurality of integrated circuit chips mounted thereon and interconnecting input and output signals of respective integrated circuit chips.
For this purposes, there is a necessity for a wiring substrate capable of having integrated circuit chips mounted with high density thereon, causing short propagation delay times inside thereof, and having small parasitic capacitance and inductance values of signal lead wiring or spread wiring extending from integrated circuit chips to through-holes and of through-holes themselves.
One of wiring substrates having such characteristics is a ceramic multilayer interconnection substrate shown in FIG. 7 of Nikkei Electronics, June 17, 1785, p. 251. In this wiring substrate, a fine signal wiring layer is formed on the surface of an alumina ceramic substrate having a power supply and ground layer by applying a thin-film process such as photolithography to polyimide resin. Owing to a lowered dielectric constant resulting from application of polyimide resin and a higher wiring density and a shortened through-hole length resulting from application of a thin film process, the above described characteristics demanded of wiring substrates are effectively realized.
At the present time, higher integration and capability of handling larger power are sought in integrated circuit chips for large computers, and integrated circuit chips of an integration class having 10,000 gates are put into practical use. For mounting chips of high integration on a wiring substrate, a large number of signal wiring layers must be formed on a large-sized substrate even if the above described substrate using thin film wiring is used.
If the wiring substrate is increased in size, wiring running in the wiring layer becomes longer and voltage drop caused by direct current resistance has a value which cannot be neglected. To improve this, the thickness of signal wiring must be made larger. However, it takes an enormously long process time to form thick wiring by using the thin film process. Therefore, it becomes disadvantageous as regards the cost to form a wiring layer by using the thin film process entirely as the number of wiring layers is increased and the substrate size is made large.
If in this case a signal wiring layer is formed by a thick film wiring process in the portion of a ceramic substrate existing in the lower portion of the thin film wiring layer, a wiring substrate can be formed at a low cost. In one method of the thick film wiring process, a conductor layer is formed on a sheet comprising a ceramic material, for example, by screen printing and then this is sintered to form thick film wiring. However, the signal wiring layer in the ceramic substrate is larger in dielectric constant than a signal wiring layer formed by applying a thin film wiring process to an organic insulation layer such as polyimide resin or an inorganic insulation layer such as SiO.sub.2, and it is not easy to form wiring and through-holes minutely.